RF Design Engineer (m/f/d)

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RF Design Engineer (m/f/d)

Apple

Location

Munich, Bavaria-Bayern, 80335, Germany

Experience

Mid

Posted

Jul 30, 2026

Apply by

August 29, 2026

Applicants

0

Early applicantEasy applyFull-timeWork from Office

Job Description

Would you like to be part of Apple’s fast-growing RF wireless design team in Munich? We are responsible for all aspects of wireless silicon development with a particular emphasis on highly integrated, power efficient designs and advanced semiconductor technologies that enable an outstanding user experience. IC design engineers work on circuit and system solutions for sophisticated wireless chips. This is a highly visible role in a fast growing silicon design group where you'll have the opportunity to make a critical impact on getting innovative consumer products to a global customer base quickly! ## Description As a RF Design Engineer at Apple, you will use your vast background in circuit design and provide PLL design solutions for wireless chips. You will collaborate with platform architects, system group, and digital design group to define the requirements for a PLL lineup based on the product requirements. You will also work with the Apple technology team and silicon foundries on process evaluation/selection for the target device. Design tasks include various analog biasing blocks, oscillators, frequency dividers and local oscillator chains. You will work with system engineering, layout, and chip integration teams to integrate the IP’s and verify the top-level functionality and performance. You also will work with RF test engineers to bring up, characterize and optimize new silicon. ## Minimum qualifications Profound experience in RF circuit design techniques. Experience with Cadence design tools. EM modelling and simulation skills. MSEE /PhD or equivalent is required. Proficiency in English is required. ## Preferred qualifications A proven track record in RF, and analog integrated circuit design, with experience in wireless PLL circuit architectures in CMOS technologies. Deep understanding in PLL system specifications and the ability to work with system architects to translate system requirements into circuit requirements at IC block level. Knowledge in fundamental RF theories and concepts, such as innovative PLL concepts and their trade-offs in key performance parameters (KPI’s), area and power efficiency. The ability to optimize the overall PLL system including EVM, blocker requirements and crosstalk mitigations. Deep technical knowledge in analysis, design, and implementation of RF wireless low-noise, broadband and power efficient PLLs, as well as frequency converting blocks. Extensive experience in simulation of RF analog key building blocks, such as oscillators, frequency dividers, phase detectors and local oscillator signal distribution chains Solid experience in optimization of RF circuit design impairments by means of highly sophisticated methods of trimming and calibration Experience in RF cross talk analysis, understanding the critical RF cross talk building laws and the according aggressor and victim analysis, translation of RF system KPI's into IC block level isolation requirements Understanding of RF device modelling, insights into packaging effects, integrated coils, supply isolations, high frequency ESD structures, and circuit layout for optimum performance. Hands-on experience in high frequency silicon characterization and debugging on chip as well as on system level. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. If you’d like more information about your EEO rights as an applicant. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

Key Responsibilities

  • Provide PLL design solutions for wireless chips.
  • Collaborate with platform architects and system groups to define PLL lineup requirements.
  • Work with technology teams and foundries on process evaluation and selection.
  • Design analog biasing blocks, oscillators, frequency dividers, and local oscillator chains.
  • Integrate IP with system engineering, layout, and chip integration teams.
  • Verify top-level functionality and performance with system engineering and layout teams.
  • Collaborate with RF test engineers to bring up, characterize, and optimize new silicon.

Requirements

  • MSEE or PhD in Electrical Engineering or equivalent

Skills Required

RF circuit designCadence design toolsEM modellingSimulationPLL designAnalog biasingOscillator designFrequency divider designLocal oscillator chain designSystem integrationChip integrationRF test engineeringCollaborationCommunicationAnalog integrated circuit designWireless PLL circuit architecturesCMOS technologiesPLL system specificationsRF theories and conceptsPLL optimizationEVM optimizationBlocker requirementsCrosstalk mitigationRF cross talk analysisRF device modellingPackaging effectsIntegrated coilsHigh frequency ESD structuresCircuit layoutHigh frequency silicon characterizationChip debugging

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