This role is for one of the Weekday's clients Min Experience: 4+ years Location: Bengaluru JobType: full-time We are looking for a SoC Verification Engineer with strong expertise in SystemVerilog and UVM to contribute to the functional verification of complex ARM-based System-on-Chip (SoC) designs. In this role, you will develop verification environments, create test scenarios, execute gate-level simulations, and drive verification closure to ensure high-quality silicon. The ideal candidate should have hands-on experience in SoC verification methodologies, UVM-based testbench development, and debugging complex simulation issues. ### Key Responsibilities ### SoC Functional Verification - Develop and execute test cases for SoC-level functional verification. - Design and enhance SystemVerilog/UVM-based verification environments. - Verify complex system-level scenarios for ARM-based SoC architectures. - Ensure functional correctness through comprehensive simulation and verification. ### Simulation & Debugging - Execute Gate-Level Simulations (GLS) to validate post-synthesis and post-layout designs. - Debug functional failures, timing issues, and low-power simulation results. - Analyze simulation waveforms and identify root causes of verification failures. - Collaborate with RTL designers to resolve design and verification issues. ### Coverage & Verification Closure - Drive functional coverage closure using coverage-driven verification methodologies. - Monitor code coverage, functional coverage, and assertion coverage metrics. - Develop constrained-random test scenarios to improve verification completeness. - Support regression execution and verification signoff activities. ### Cross-Functional Collaboration - Work closely with RTL Design, Physical Design, DFT, and Architecture teams throughout the development cycle. - Participate in verification planning, reviews, and debugging discussions. - Contribute to reusable verification components and methodology improvements. - Document verification plans, test cases, and verification results. ### Required Qualifications - Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. - Strong hands-on experience in SystemVerilog and UVM-based verification. - Experience developing and maintaining UVM testbenches. - Good understanding of ARM-based SoC architectures and system-level verification scenarios. - Knowledge of AMBA bus protocols, including APB, AHB, and AXI. - Experience executing and debugging Gate-Level Simulations (GLS). - Understanding of low-power verification concepts and low-power simulations. - Strong debugging, analytical, and problem-solving skills. - Excellent communication and collaboration abilities. ### Preferred Qualifications - Experience with Python or Perl scripting for verification automation. - Familiarity with industry-standard simulation and waveform debugging tools. - Exposure to assertion-based verification and functional coverage methodologies. - Knowledge of verification automation frameworks and regression management. ### Must-Have Skills - SoC Verification - SystemVerilog - UVM - UVM Testbench Development - Gate-Level Simulation (GLS) - ARM-Based SoC Verification - APB - AHB - AXI - Functional Coverage ### Good-to-Have Skills - Python - Perl - Low-Power Verification - Assertion-Based Verification (SVA) - Verification Automation - Waveform Debugging - Regression Management