𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀 𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟲𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟬-𝟲𝟬 𝗟𝗣𝗔) Experience: 5+ yrs Location: Bengaluru, Karnataka, India, India Job Type: Full-time We are seeking an experienced Static Timing Analysis (STA) Engineer to drive timing closure and sign-off activities for advanced SoC designs across cutting-edge semiconductor technology nodes. This role is ideal for professionals with deep expertise in Static Timing Analysis, timing optimization, and sign-off methodologies, who thrive in a collaborative VLSI development environment. As an STA Engineer, you will be responsible for performing comprehensive timing analysis, driving timing convergence, implementing Engineering Change Orders (ECOs), and working closely with Physical Design, Synthesis, and Clock Tree Synthesis (CTS) teams to ensure successful tape-outs. You will play a critical role in delivering high-performance, reliable, and timing-clean semiconductor designs. ### Key Responsibilities - Perform block-level and full-chip Static Timing Analysis (STA) for complex, high-performance SoC designs. - Drive timing closure throughout the design lifecycle, including pre-layout and post-layout stages. - Analyze and resolve setup, hold, recovery, removal, maximum transition, maximum capacitance, and fanout violations. - Execute MCMM (Multi-Corner Multi-Mode) timing analysis and optimization to ensure robust design performance. - Collaborate closely with Physical Design, Synthesis, CTS, Routing, and ECO teams to achieve timing convergence. - Generate, review, and interpret timing reports while identifying and resolving critical timing paths. - Implement and validate ECOs to improve timing performance and support design optimization. - Support timing sign-off activities, including signal integrity (SI) analysis and low-power timing verification. - Contribute to successful tape-outs by ensuring compliance with timing, quality, and design requirements. - Develop automation scripts and improve STA workflows to enhance productivity and design efficiency. ### What Makes You a Great Fit - 5+ years of hands-on experience in Static Timing Analysis (STA) for advanced SoC designs. - Strong expertise in Synopsys PrimeTime and timing sign-off methodologies. - Proven experience with MCMM timing analysis, timing closure, and sign-off flows. - Deep understanding of timing constraints (SDC), clock architecture, timing exceptions, and optimization techniques. - Hands-on experience with PrimeTime SI for signal integrity analysis. - Strong knowledge of Physical Design processes, including Floorplanning, Placement, CTS, Routing, and ECO implementation. - Experience working on advanced technology nodes such as 5nm, 7nm, 12nm, 16nm, or 28nm. - Proficiency in TCL and Shell scripting for automation and workflow optimization. - Strong debugging, analytical, and problem-solving skills with attention to detail. - Exposure to tools such as Synopsys ICC2 or Cadence Innovus, along with knowledge of OCV, AOCV, POCV, LVF, CPPR, Crosstalk, IR Drop, EM analysis, UPF/CPF, or high-speed interface timing, will be an added advantage.