This role is for one of the Weekday's clients Salary range: Rs 1000000 - Rs 1500000 (ie INR 10 - 15 LPA) Min Experience: 4+ years Location: Bengaluru JobType: full-time We are looking for a SoC Integration Engineer to drive the end-to-end integration of complex SoC blocks from specification through signoff. In this role, you will be responsible for executing SoC integration flows, ensuring design quality, and collaborating closely with RTL Design, Verification, Physical Design, and DFT teams to deliver high-performance silicon. The ideal candidate should have strong experience with RTL integration, synthesis, lint, CDC analysis, timing constraints, and industry-standard EDA tools. ### Key Responsibilities ### SoC Block Integration - Own the end-to-end integration of assigned SoC blocks from specification through signoff. - Ensure designs meet functional, performance, power, and area targets. - Integrate RTL and validate design readiness for downstream implementation. - Manage block releases and support milestone deliveries. ### SoC Design Flow - Execute complete SoC integration flows using industry-standard EDA tools. - Perform RTL quality checks using SpyGlass Lint. - Execute Clock Domain Crossing (CDC) analysis and resolve violations. - Perform RTL synthesis using Synopsys Design Compiler (DC). - Support VCLP (Verification, Constraint, Lint, and Power) flow execution. - Maintain high-quality design collateral throughout the integration lifecycle. ### Power & Constraint Management - Support power-aware design methodologies using Unified Power Format (UPF). - Define and maintain power domains, isolation strategies, retention logic, and related power intent where applicable. - Develop and maintain accurate timing constraints (SDC) and other design constraints. - Ensure constraint consistency across design, verification, and physical implementation flows. ### Cross-Functional Collaboration - Work closely with Verification, Physical Design, DFT, and Architecture teams throughout the development cycle. - Provide technical guidance on timing constraints, power intent, lint issues, and synthesis-related challenges. - Support debug and issue resolution during integration and implementation. - Prepare technical documentation, design specifications, release notes, and constraint documentation. ### Debugging & Quality - Debug RTL, synthesis, timing, lint, and CDC issues using industry-standard debug tools. - Perform root cause analysis and implement corrective actions. - Continuously improve design quality and integration methodologies. - Contribute to process improvements and automation initiatives. ### Required Qualifications - Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field. - Strong experience in SoC Block Integration and RTL integration. - Hands-on expertise with SpyGlass Lint, CDC analysis, Synopsys Design Compiler (DC), and VCLP flows. - Strong knowledge of RTL synthesis and timing constraints (SDC). - Proficiency in Verilog, SystemVerilog, or VHDL. - Experience using Verdi or equivalent RTL debugging tools. - Strong debugging, analytical, and problem-solving skills. - Excellent communication and cross-functional collaboration abilities. ### Preferred Qualifications - Experience with UPF (Unified Power Format) and power-aware design methodologies. - Understanding of power domain definition, isolation, and retention strategies. - Exposure to Physical Design and DFT implementation flows. - Experience working on complex consumer or high-performance SoC projects. - Knowledge of automation and scripting for design flow optimization. ### Must-Have Skills - SoC Integration - RTL Integration - SpyGlass Lint - CDC Analysis - Synopsys Design Compiler (DC) - VCLP - Verilog - SystemVerilog - Timing Constraints (SDC) - Verdi Debugging ### Good-to-Have Skills - UPF (Unified Power Format) - Power Domain Design - Physical Design Collaboration - DFT Flow - Scripting (TCL, Perl, Python) - SoC Architecture - Design Automation - Timing Analysis